It appears you have JavaScript disabled within your browser. Some functions on this page will not work unless you log in.

See an Error?

LS1012ASE7KKB

Name: NXP LS1012ASE7KKB
Brand: NXP Semiconductors
SKU: 771-LS1012ASE7KKB
Price: 33.02 EUR
Availability: InStock

Images are for reference only
See Product Specifications

Mouser No:

771-LS1012ASE7KKB

Mfr. No:

LS1012ASE7KKB

Mfr.:

NXP Semiconductors

Description:

Microprocessors - MPU LS1012A - ST WE PFE GbE PCIe SATA 1G R2

Datasheet:

LS1012ASE7KKB Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about NXP Semiconductors LS1012ASE7KKB

Delivery Alerts:

This product may require additional documentation to export from the United States.

In Stock: 334

Stock:: 334 Can Dispatch Immediately

An unexpected error occurred. Please try again later.
Factory Lead Time:: 26 Weeks Estimated factory production time for quantities greater than shown.

Enter Quantity:

Minimum: 1 Multiples: 1

Unit Price:

-,-- €

Ext. Price:

-,-- €

Est. Tariff:

Pricing (EUR)

Qty.	Unit Price	Ext. Price
	33,02 €	33,02 €
	26,90 €	269,00 €
	25,37 €	634,25 €
	24,60 €	2.460,00 €
	23,38 €	3.927,84 €

.hidden-for-nojs { display: none; } .pull-right-nojs { justify-content: flex-end; }

Product Attribute	Attribute Value	Select Attribute
Manufacturer:	NXP
Product Category:	Microprocessors - MPU
Delivery Alerts:	This product may require additional documentation to export from the United States.
RoHS:
Core:	ARM Cortex A53
Number of Cores:	1 Core
Data Bus Width:	64 bit
Maximum Clock Frequency:	1 GHz
Package/Case:	VFLGA-211
L1 Cache Instruction Memory:	32 kB
L1 Cache Data Memory:	32 kB
Operating Supply Voltage:	900 mV
Series:	LS1012A
Mounting Style:	SMD/SMT
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 105 C
Packaging:	Tray
Brand:	NXP Semiconductors
Country of Assembly:	TW
Country of Diffusion:	TW
Country of Origin:	TW
Data RAM Size:	128 kB
Instruction Type:	Floating Point
Interface Type:	I2C, I2S, JTAG, SDIO, SPI, UART
L2 Cache Instruction / Data Memory:	256 kB
Memory Type:	DDR3L
Moisture Sensitive:	Yes
Product Type:	Microprocessors - MPU
Factory Pack Quantity:	168
Subcategory:	Microprocessors - MPU
Tradename:	QorIQ
Watchdog Timers:	Watchdog Timer
Part # Aliases:	935357526557
Unit Weight:	164,300 mg

Products found:

To show similar products, select at least one checkbox

Select at least one checkbox above to show similar products in this category.

Attributes selected: 0

Filter Document:

Datasheet

LS1012ASE7KKB Datasheet (PDF)

TARIC:: 8542319000
CNHTS:: 8542319091
CAHTS:: 8542310000
USHTS:: 8542310050
ECCN:: 5A002.a.1

QorIQ Layerscape LS1012A Low Power Comm ICs

NXP QorIQ Layerscape LS1012A Low Power Communications Processor is optimized for battery-backed or USB-powered, space-constrained networking and IoT applications. The LS1012A processor integrates a single ARM Cortex-A53 core running up to 800MHz with L1 and ECC-protected L2 caches. The device incorporates the same trust architecture and software compatibility of the higher-tier QorIQ LS family devices. The LS1012A processor features 32KB of L1 instruction and data cache and 256KB of coherent L2 cache. This device features a three-lane, 6GHz multi-protocol SerDes that provides support for high-speed interfaces. Support includes up to two Gigabit Ethernet ports, a DMA-controlled PCI Express® generation 2.0 port, and one SATA 3.0 port. The LS1012A also features dual USB controllers—one supporting SuperSpeed USB 3.0 with integrated PHY, the other supporting USB 2.0 functions. Additional interfaces include QuadSPI and support for SD/MMC. This processor provides intelligent integration and extreme power efficiency in a small 9.6mm x 9.6mm package for fanless, small form factor networking and IoT applications.

Layerscape Architecture

NXP Layerscape Architecture is the underlying system architecture of the QorIQ® LS series processors. The architecture enables next-generation networks with up to 100Gb/s performance and enhanced packet processing capabilities. Design effort is simplified with a standard, open programming model and a software-aware architecture framework. This design enables customers to fully exploit the underlying hardware for maximum optimization, with the capability to easily adapt to network changes for real-time soft control over the network. A uniform hardware and software model provides the compatibility and scalability required for designing end-to-end networking equipment from home-to carrier-class products. The core-agnostic architecture incorporates the optimum core for the given application: Arm® cores or Power Architecture® cores.